A Read-Only Memory (ROM) cell is well known in the art. Typically, a ROM cell comprises a single MOS transistor having a first region, and a second region separated from one another by a channel. A gate is positioned over the channel and is insulated therefrom. A voltage is applied to the gate and the voltage controls the conduction of the channel. A single bit ROM cell means that the VTH or the voltage of the threshold by which the transistor turns on has been adjusted by an implantation step. When an appropriate voltage is applied to the gate, the source, and the drain, either the ROM cell is turned on or is turned off. Thus, the ROM cell is capable of storing a single bit.
A ROM cell capable storing multi-bits is also well known in the art. The advantage of a multi-bit ROM cell is that the density of the memory storage can be increased. Referring to FIG. 1, there is shown a typical process for manufacturing a ROM cell for storing one of a plurality of bits. The ROM cell 10 has a source 12, a drain 14 spaced apart from the source 12 and a channel 16 therebetween. The source 12 and drain 14 are in a substrate 20. Typically, the substrate 20 is of a p-type conductivity. Thus, the source 12 and drain 14 are of n-type. Of course, the substrate 20 can also be a well within the substrate 20. A gate 22 is spaced apart and insulated from the channel 16 by an insulation layer 24. If the ROM cell 10 is to store, e.g. two bits or four possible states, the ROM cell 10 would have to undergo potentially as many as three masking steps for implantation. One of the possible states for the ROM cell 10 is in which the VTH (designated as VT1) is the highest. In that event, no additional implant of N type material is made into the channel region 16 thereby affecting the VTH. The next higher level of VTH would be an implant of donor (n−) species into the channel region 16. A third and fourth state would be where yet even higher dosages of donor (n−) species are implanted into the channel, lowering VTH. Thus, if the ROM cell 10 were to store one of a possible of four states representing two bits, potentially, as many as three additional mask steps would be required to implant the channel region 16 to change the VTH thereof. An array of multi-bit ROM cells is also well known in the art. However, similar to the foregoing description with regard to the manufacturing of a multi-bit ROM cell, the array is made with potentially as many as M−1 implants, with M as the total number of possible states.
An MOS transistor is also well known in the art. Typically, an NMOS transistor 30, such as the one shown in FIG. 2A, comprises a source region 32, a drain region 34 and a substrate 20. Again, the substrate typically is of P type conductivity and the source 32 and drain 34, are of N type. Again, the source 32 and drain 34 can be in a well, with the well in the substrate 20. Further, the conductivity of the source 32, drain 34 and of the substrate (or well) can be reversed, and the transistor 30 would be PMOS type. A channel 36 is between the source 32 and drain 34. As the scale of integration increases, i.e., as the size of the MOS transistor 30 decreases, typically the channel region 36 will have three portions: each labeled as 1, 2 and 3 in FIG. 2A. A gate 22 is spaced apart from at least the second portion of the channel 36 by an insulation layer 24. Because of the scale of integration, LDD (lightly doped drain) structures 38 and 40 are formed in portions 1 and 3, with portion 1 located adjacent to and connected with the source region 32 and portion 3 located adjacent to and connected to the drain region 34. The second portion is between the first and third portions. The LDD like structures in portions 1 and 3, shown in FIG. 2A, are of the same type of conductivity as the source and drain 32 and 34, respectively. Thus, in the event the substrate 20 is of P type and the source and drain 32 and 34 are of N type, the LDD like structures (also known as “extensions”) in portions 1 and 3 are also N type. The function of the extensions is to decrease the resistance between the source 32 and the drain 34, which increases the turn on current. Thus, a removal of either one or both of the extensions 38 and 40 in FIG. 2A would decrease the current flow between the source and drain.
In addition, because of the increased scale of integration, halo regions 42 and 44 have also been implanted into portions 1 and 3. A halo portion 42 or 44 is an increase in conductivity of the same type as the substrate 20. Therefore, again, if the substrate 20 is of the p-type, and the source and drain 32 and 34 are of n-type, with the extensions 38 and 40 also of n-type, the halo regions 42 and 44 are of p-type, but with a concentration greater than the substrate 20. The halo regions 42 and 44 prevent punch through. The effect of adding halo regions 42 and 44 is to increase the VTH, which decreases the turn off current. Thus, removal of the halo regions 42 and 44 would reduce the VTH thereby increasing current flow between the source drain 32 and 34 respectively. This is shown in FIG. 2B. One can choose to include either the halo regions 42 and 44 or the extensions 38 and 40, or both by selecting the biases to emphasize one effect versus another effect. If standard CMOS masks are not used, however, then only one effect, i.e. either halo regions 42 and 44 or extensions 38 and 40 is chosen.
As can be appreciated, the formation of each of the extensions 38 and 40 and of the halo regions 42 and 44 requires an additional masking step.
Accordingly, it is one object of the present invention to make an array of multi-bit ROM cells in which the operations of implant and masking is reduced compared to the method of the prior art.